Technical Field
The present invention generally relates to three-dimensional semiconductor transistors and the fabrication thereof. More particularly, the present invention relates to gate contacts for three-dimensional semiconductor transistors and the fabrication thereof in the active region without gate-to-source/drain shorts.
Background Information
Conventional fabrication of FinFET semiconductor structures places the gate contact outside of the active region, to avoid gate contact to source/drain contact short circuits. However, doing so may result in design restrictions and uses more area. As semiconductor devices continue to shrink, the loss of semiconductor real estate becomes more and more of an issue.
Thus, a need exists to reduce the footprint of a three-dimensional semiconductor transistor while also allowing for downward scaling.